A time-to-digital converter (hereinafter referred to as a TDC) is conventionally known that outputs a phase difference between two clock signals as a digital value.
For example, the TDC delays a clock signal with multiple delay elements connected in series to detect a phase difference between two clock signals. For example, in a known related technique for the TDC, a phase difference between two clock signals is detected in two stages of fine and coarse phase differences (see. e.g., Published Japanese-Translation of PCT Application, Publication Nos. 2009-527158 and 2011-518534).
For example, in a known technique for an A/D converter, a pulse signal is delayed by multiple delay elements depending on a delay time corresponding to analog input voltage or amplitude of analog input current so as to convert an analog signal to a digital signal based on output signals output from the respective multiple delay elements (see., e.g., Japanese Laid-Open Patent Publication No. 2010-183176).
For example, a delay-locked loop (DLL) may be utilized for reducing variations of delay amounts of delay elements due to process voltage temperature (PVT) (see., e.g., “Jitter Transfer Characteristics of Delay-Locked Loops Theories and Design Techniques”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 38, No. 4, April 2003)
However, variations in the delay of delay elements due to PVT cause a problem of deterioration in accuracy of phase detection from two clock signals by the TDC.